Digital-to-analog converters are widely used in the field of circuit electronics and are implemented with either discrete or integrated elements. Abundant literature is available on the subject.
From U.S. Pat. No. 5,376,935, which is hereby incorporated by reference, a digital-to-analog converter is known which includes a plurality of electrically programmable floating gate transistors, each having an electrically programmable threshold voltage. Each of the transistors has its source coupled to ground, its control gate coupled to an output node, and its drain coupled to the output node via one of a plurality of switching circuits. The output node is coupled to a voltage source via a load circuit. An input circuit decodes a digital input signal to selectively generate one of a plurality of control signals at a time in accordance with the digital input signal. Each of the control signals is for one of the switching circuits. When a transistor is coupled to the output node, the voltage level of the output node is equal to the threshold voltage of that transistor.
From A. Kramer et al., "Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementation of Neural Networks," IEDM Tech. Dig., pages 17.6.1-4, December 1994, a charge injection circuit is known which is based on the use of a floating gate MOS transistor connected as a capacitor, wherein the injected/extracted charge is dependent on the threshold voltage of the transistor and the width of the voltage step supplied to its control terminal.
The article also brings out a limitation of that circuit, namely the fact that floating gate MOS transistors of the standard type have a very high parasitic overlap capacitance which dominates over the channel capacitance. This is a cause of considerable error in the charge injection. One way of partially solving this problem, as suggested in the article, is to use a MOS transistor of a particular type, that is a MOS transistor having its floating gate extended outside the channel area (included between the source and the drain areas) in the vertical direction relative to the channel length, but substantially non-overlapping the source and drain areas. Such a MOS transistor is also known, defined as a non-volatile memory cell, from Patent Application EP 0 661 756 A1. In this way, the channel capacitance is increased with respect to the parasitic capacitance, but not to a sufficient extent to make it negligible.